1. Field of the Invention
The present invention relates to a peak hold circuit favorably applied to a light receiving circuit for optical interconnects and a constant-voltage generating circuit favorably applied to a laser driving circuit.
2. Discussion of the Background
A technique of detecting an analog signal at high speed and converting it into a digital signal has recently been essential to a multimedia instrument and the like. A sample hold circuit is necessary for an analog-to-digital conversion. As one method of the sample hold circuit, there is a combination of a high-speed switch circuit and a voltage holding capacitor, for catching analog signals sampled in a short time slot and holding their peak values.
Of circuits for processing digital signals only, there are a circuit for optical telecommunications and optical interconnects, a signal readout circuit for a magnetic memory and semiconductor memory, and the like, the input signal levels of which are varied and unclear. In these circuits, it is important that an input signal level of the preamplifier is detected automatically to determine the optimum operation point and minimize a distortion of waveform of a reproduced pulse.
In order to minimize the distortion, an automatic discrimination type waveform reproduction circuit has been employed which detects and normalizes a peak level of an input pulse signal to always discriminate the pulse signal by half the amplitude of the pulse signal irrespective of variations in the level of the input pulse signal.
It is a peak hold circuit that is important in common to the foregoing examples. In particular, it is desirable for a circuit for processing a signal with an arbitrary pattern, such as the optical interconnection, to respond to a burst waveform and it is important to respond at high speed of not less than nanoseconds in order to correctly detect and hold a peak value of the first-input pulse. Recently there have been great demands that the peak hold circuit should be relatively small in size or compact so as to be incorporated into an IC without any external capacitor. Also there have been demands for low power consumption in order to incorporate the peak hold circuit into a multichannel array.
The fundamental arrangements of known prior art peak hold circuits are illustrated in FIGS. 1 and 2 and the operation principle of each circuit is as follows. In the circuit of FIG. 1, a pulse input to an input terminal of a differential amplifier constituted of transistors Q100 and Q101, is compared with an output voltage of the peak hold circuit and, if the voltage of the input pulse is higher than the output voltage, an error is amplified and the base voltage of a switching transistor Q102 is increased. Thus, the transistor Q102 is turned on to start charging a voltage holding capacitor C100. When an output voltage of an emitter follower circuit of a transistor Q103 reaches the voltage of the input pulse, the base voltage of the transistor Q102 is lowered to cut off the current flowing into the transistor Q102. If the top voltage of the input pulse is maintained until the current is cut off the voltage with which the voltage holding capacitor C100 is charged, becomes equal to the peak voltage of the input pulse.
Since the leak peak current of the transistor Q103 is low, the time constant of discharging of the capacitor is large and its peak voltage is maintained.
The operation of the switching transistor Q102 will be described in more detail. The transistor Q102 is a bipolar transistor and thus has a characteristic of causing a current to flow exponentially with respect to a base-to-emitter voltage. When the amplitude of input voltage of the base is small, the dynamic impedance is high, the injected current is small, and the peak transit time is long. On the other hand, when the amplitude exceeds a certain value, the impedance is drastically lowered and the charging time is too short, with the result that a feedback is delayed and so is the cutoff of the switching transistor, thus causing an overshoot of the output voltage.
Consequently, an input voltage range for normally operating the circuit is restricted, and it is difficult to widen an input dynamic range. If the input voltage is too high, a collector current may flow through the transistors beyond a tolerable range, and the cutoff frequency may decrease, thereby causing a delay in response.
A circuit capable of excluding the above drawbacks to some extent, is shown in FIG. 2. In the circuit of FIG. 2, a voltage holding capacitor C100 is charged with a current which is almost proportional to the amplitude of an error voltage by a current output amplifier using a pnp transistor in place of a switch of an npn transistor (shown in FIG. 1) with drastically changing impedance. In the circuit of FIG. 2, a power supply voltage needs to be higher than that of the circuit of FIG. 1 and the pnp transistor should satisfy a high speed operation.
In general, however, the bandwidth of the pnp transistor is about one-tenth of that of the npn transistor; thus, the circuit of FIG. 2 has an essential problem that a high-speed operation cannot be satisfied.
The problem of the circuit shown in FIG. 1 on principle is an exponentially, nonlinear response to an input voltage of a switching transistor. However, this problem can be resolved if, as in the circuit of FIG. 2, the npn switching transistor is operated so as to exhibit a linear response to the input voltage.
A high gain feedback amplifier may be useful for the peak hold circuit in order to linearly operate an element originally having a remarkably nonlinear characteristic. In this case, usually, there occurs a problem that a high-speed operation cannot be carried out due to a delay in a high gain feedback as well as a problem that a large-sized circuit increases in chip area and thus in power consumption.